The present invention relates to semiconductor devices, and more specifically to effective technology to be utilized for dynamic RAM (random access memory) having a multiple bit test function.
Regarding test circuits where a plurality of data lines corresponding to a plurality of memory cells are coupled to one common data lines whereby decisions of coincidence or non-coincidence of storage information of the plurality of memory cells coupled to one word line are carried out, and multiple bit parallel test systems using such test circuits, disclosure is seen, for example, in U.S. Ser. No. 07/228,022, Aug. 4, 1988 and U.S. Ser. No. 346,48, Jun. 12, 1989. Also regarding technology relating to dynamic RAMs containing a redundancy circuit for defect relief, disclosure is seen, for example, in U.S. Pat. No. 4,849,939, Jul. 18, 1989.